Integrated circuits are used in a wide range electronic devices produced by a large number of device manufacturers. In practice, ICs are seldom manufactured (fabricated) by the electronic device manufacturer. Instead ICs are manufactured by an IC foundry to the specifications of the electronic device manufacturer. The design of the IC is usually the result of corroboration between the device manufacturer and the IC foundry.
The design and manufacture of an application-specific IC, or ASIC, is usually a long and tedious process, requiring development of a hardware description language (HDL) description of the circuit, usually in a synthesizable register transfer language (synthesizable RTL), synthesizing the RTL description to a technology library of components, and ultimately fabricating the circuit into an IC chip. During the process, testing and re-designing is necessary to optimize cell placement to meet physical constrains, wire routing and timing constraints. The process is time consuming and costly.
To reduce the time and cost of development of ASICs, IC foundries have developed standard, or base, platforms containing silicon layers of an IC, but without metal interconnection layers. The silicon layers are configured into gates that can be configured into cells using tools supplied by the IC foundry. The chip designer designs additional metal layers for the base platform to thereby configure the chip into a custom ASIC employing the customer's intellectual property. The IC foundry ordinarily supplies tools to the IC designer to enable the designer to quickly and accurately configure the base platform to a custom ASIC compatible with the foundry's fabrication technology. An example of such a configurable base platform is the RapidChip® platform available from LSI Logic Corporation of Milpitas, California. The RapidChip platform permits the development of complex, high-density ASICs in minimal time with significantly reduced design and manufacturing risks and costs.
The design effort can be considered as encompassing several stages. After the chip size and the placement of the I/O cells has been selected, the megacells, including memories, are placed. Thereafter, standard cells are place to complete the chip. The present invention deals with placement of memories, and particularly to mapping user's custom memories to standard or basic memories that are incorporated into the base platform.
Consider a base platform containing a predetermined number of basic memories of predetermined types. The design created by the IC designer may contain user-defined memories that are different from the basic memories. The present invention is directed to techniques for mapping user-defined memories to basic memories so that the user-defined memories can be implemented in basic memories on the base platform.